This invention relates to multi-channel communication circuitry for integrated circuits such as programmable logic devices (“PLDs”), and more particularly to circuitry for facilitating synchronizing the operation of different numbers of such channels.
References such as Aung et al. U.S. Pat. No. 7,227,918, Lee et al. U.S. Pat. No. 6,650,140, Venkata et al. U.S. Pat. No. 6,750,675, Venkata et al. U.S. Pat. No. 6,854,044, Lui et al. U.S. Pat. No. 6,724,328, Venkata et al. U.S. Pat. No. 7,305,058, Venkata et al. U.S. Pat. No. 7,272,677, Lam et al. U.S. Pat. No. 7,028,270, Venkata et al. U.S. Pat. No. 7,131,024, Shumarayev U.S. patent application publication 2007/0047667, and Shumarayev et al. U.S. Pat. No. 7,525,340, show the inclusion of multi-channel transceiver circuitry on integrated circuits such as PLDs, field-programmable gate arrays (“FPGAs”), and the like. For convenience herein, all integrated circuits to which the invention is or can be applied will generally be referred to as PLDs. This is done only for convenience and is not intended as a limitation.
Different communication protocols require use of different numbers of channels working together. Heretofore, some PLDs provided the channels for such communication in groups of four (so-called quads). Circuitry for allowing various numbers of channels in a quad to be used together was provided in the quad. But if more than four channels were required to work together, then synchronization between the outputs of the quads tended to be a task for circuitry downstream from the quads (e.g., the programmable logic core circuitry of the device).
The interest in multi-channel communication employing more than four channels (e.g., eight channels) continues to increase. This makes it less and less desirable to require use of core logic circuitry for synchronizing the outputs of two (or more) quads that are being used to provide communication links that employ more than four channels. On the other hand, other users of a PLD product may still be interested in using only four or fewer channels in any particular communication link. It would therefore be wasteful to enlarge the quads on a device to include more than four channels (e.g., eight channels). Instead, better ways are needed to allow two (or more) quads to work together when a user wants to implement a communication link employing more than four channels (e.g., eight channels).
In achieving the foregoing, it can be desirable to preserve modularity of the circuitry. By modularity it is meant that two (or more) instances of the circuitry are identical or substantially identical. Modularity facilitates circuit design and verification, and it may even facilitate circuit use (e.g., because timing tends to be uniform from module to module). Modularity may be desirable on a channel basis (i.e., from one channel to the next) and/or a quad basis (i.e., from one quad to the next).